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Jaemin Seo

M.S. -Ph.D. student of CSDL

Education

M.S. -Ph.D in Electrical Engineering

Pohang University of Science and Technology(POSTECH)
Aug. 2021 - Present

B.S. in Electrical Engineering

Pohang University of Science and Technology(POSTECH)
Mar. 2017 - Aug. 2021

Languages

  • Korean (Native)
  • English (Professional)

Interests

  • Physical Design Optimization
  • VLSI EDA
  • FPGA EDA

About Theme

Career Profile

Jaemin Seo is currently M.S. -Ph.D student in the Department of Electrical Engineering in Pohang University of Science and Technology(POSTECH), Korea. He is working with Professor Seokhyeong Kang in CAD & SoC Design Lab(CSDL).

His research interest includes EDA(Electronic Design Automation) flow, ML-CAD (Machine Learning Computer Aided Design), VLSI(Very-Large-Scale Integration) physical design.

Experiences

Graduated Student Researcher

July 2021 - Present
CAD & SoC Design Lab(CSDL) in POSTECH, Prof, Seokhyeong Kang

Projects

Intel PSG Cloud Scale Quartus - Intel, UCSD, May.2022 - Present
Security Closure of Physical Layouts (ISPD Contest 2022) - New York University (NYU), March.2022
Artificial Intelligence (AI) Model for Predicting Display Panel Performance. - LG Display, Aug.2021 - Present

Publications

Skills & Proficiency

Python

Linux

Verilog

C/C++

Matlab